In the manufacture of integrated circuits, devices such as transistors are formed on a wafer and connected together using multiple metallization layers. The metallization layers include vias and interconnects that function as electrical pathways to interconnect the devices. Contacts are used to connect the vias and interconnects to the source, drain, and/or gate of the devices.
In some circumstances, an interfacial layer is formed between the contacts and the source, drain, or gate of the devices. By way of example, a nickel (Ni) metal and a silicidation process may be used to form a nickel silicide (NiSi) interfacial layer.
Unfortunately, the Schottky barrier height of the NiSi interfacial layer is not uniform for both n-type and p-type devices. Indeed, the Schottky barrier height is about 0.43 electron Volts (eV) for a p-type device and about 0.67 eV for an n-type device incorporating the NiSi interfacial layer. This asymmetrical Schottky barrier height for n-type and p-type devices is not particularly suitable when the interfacial layer faces a high mobility material (e.g., germanium (Ge), gallium antimonide (GaSb), indium arsenide (InAs), etc.).
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.